School catering supply chains: study on 5 cases

This study presents accurate data on the school catering systems of five different municipalities which decided to invest on service quality and sustainable development. The aim is to provide a compendium to be considered by other local authorities and then used as an educational tool for drafting new templates for tender specifications. Regional laws as drivers for promoting organic consumption in school canteens and waste reduction through self service systems are two examples of interesting models for sustainable school food catering. This work does not present a unique best practice model but constellations of reference models for each different situation: in such way each municipality can consult the most fit case study and search the best solution according to specific variables

Main constraints in developing public organic procurement

The present study investigates how to increase and improve school catering supply chains, to understand hindering factors and their perception in order to reveal drivers and constraints for POP. These include policy implementation instruments, changed values and attitudes, healthy nutrition policies, supply chain bottle necks, premium prices (to producers), successful procurement strategies and certification procedures. This work is based on a two-step survey concerning the Italian school food service system. Initially questionnaires were submitted to a qualified group of 50 producers and 50 caterers (managers of national and international companies of food service for school, local administrators who manage food services for the schools). The results of the questionnaires have subsequently been the basis to plan in-depth interviews with few decision makers who could represent both caterers and producers. The aim of this second step being to view how identified problems could be solved. The results show how the understanding and the acceptance of the organic food concept among the catering staff is crucial for the degree of success in each step of public organic procurement. The introduction of organic food in serving outlets needs appropriate support (such as qualification of key actors and a specific financial support). Other key aspects in this regard are laws and regulations promoting the procurement of quality food, policy interventions tackling more than one aspect of the problem, education programs, calls for tenders, negotiated procurement contracts and quality standards

The university radio in Argentina. The case of the station of the National University of Avellaneda

Este artículo aborda la historia y la situación de la radio universitaria argentina en la actualidad, los aspectos de la programación de estas emisoras, su vínculo con Internet y las nuevas tecnologías, y su desarrollo en Argentina a partir del trabajo en una red nacional de radiodifusoras, recuperando las principales aportaciones teóricas en este sentido. Posteriormente, el trabajo se enfoca en el estudio de caso de Radio UNDAV, la emisora de la Universidad Nacional de Avellaneda, Argentina, puesta en marcha en el año 2011. En este sentido, se da cuenta de la experiencia de esta emisora en torno a los aspectos teóricos abordados en la primera parte del artículo y a partir de un estudio documental, un análisis de la programación, encuestas a integrantes de los programas y una recopilación de los mecanismos de articulación académica implementados. Finalmente, se exponen a modo de conclusión, una serie de premisas en torno a los resultados obtenidos.This article addresses the history and situation of Argentine university radio today, the aspects of the programming of these stations, their link to the Internet and new technologies, and their development in Argentina through work on a national network of radio broadcasters , recovering the main theoretical contributions in this sense. Subsequently, the work focuses on the case study of Radio UNDAV, the station of the National University of Avellaneda, Argentina, launched in 2011. In this sense, it is reported the experience of this station around the theoretical aspects addressed in the first part of the article and from a documentary study, an analysis of programming, surveys of program members and a compilation of the mechanisms of academic articulation implemented. Finally, a series of premises based on the results obtained are presented as a conclusion

X86_64 vs Aarch64 Performance Validation with COTSon

In this study, we provide a set of architectural parameters for the HPLabs COTSon simulator that can be used to model existing processors, such as the Intel i7700 (X86_64 architecture) and the ARM A53 (Aarch64 architecture). We carry out an initial validation, by comparing the execution time while performing the weak scaling of the architecture, in the case of two common benchmarks. We use the Recursive Fibonacci and Matrix Multiplication benchmarks for simplicity. By using the simulator, we can then further study the sensitivity of the architecture and derive which features may matter most to evaluate the performance. Our goal here is to verify that the COTSon simulator can be used to model both the X86_64 and Aarch64 architectures. Based on this validation study, we have the possibility to analyze the bottlenecks and desirable microarchitectural features of modern architectures

Manual Therapy in Diabetic Patients with Tibio-tarsal Dorsiflexion Deficit and Forefoot Overload: A Case Report

Introduction: Limitation of tibio-tarsal joint mobility in diabetic patients can occur within a few years of diagnosis, even in young patients. This joint movement deficit is believed to be due to stiffness in muscles, tendons, joint capsules, ligaments, and skin. With this in mind, the aim of this study is to design an experimental protocol of orthopedic manual therapy and therapeutic exercise in the future for subjects with diabetes, reduced joint mobility, and subsequent insufficient dorsal flexion of the tibio-ankle, and to test the reduced avampodalic pressure that correlates with an increased ulcerative risk. Case presentation: A patient aged 64, male, overweight, family history of type II diabetes, self-employed, and diagnosed with diabetes type 2. Results: The patient was evaluated with inertial motion sensors, a Baropodometric platform, a Lounge test, and MWM. Already after the first session, an improvement in plantar pressures was observed with a decrease both in the peaks from 413.6 Kpa to 99 Kpa in both feet and in the average plantar pressures from 129.8 Kpa to 54.5 Kpa for both feet with a decrease in plantar pressures at the forefoot from 43.7 % to 33.2 %. Tissue elasticity was assessed with the Lunge Test, and increased from 8 cm to 9.5 cm. Conclusion: The results suggest that the role of manual treatment combined with an exercise program could increase tarsal dorsiflexion and consequently decrease plantar pressures

ExploitingDMAto enablenon-blockingexecution inDecoupledThreadedArchitecture

DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on existing simple cores (in-order pipelines, no branch predictors, no ROBs). In DTA, the local variables and synchronization data are communicated via a fast frame memory. If the compiler can not remove global data accesses, the threads are excessively fragmented. Therefore, in this paper, we present an implementation of a pre-fetching mechanism (for global data) that complements the original DTA pre-load mechanism (for consumer-producer data patterns) with the aim of improving non-blocking execution of the threads. Our implementation is based on an enhanced DMA mechanism to prefetch global data. We estimated the benefit and identified the required support of this proposed approach, in an initial implementation. In case of longer latency to access memory, our idea can reduce execution time greatly (i.e.,11xforthezoombenchmarkon8processors)compared to the case of no-prefetching. 1

Organic and conventional public food procurement for youth in Italy

This report describes the political organisation and policies about public organic procurement in Italy, especially within school catering, and how organic products are utilized in this sector. The report is produced within the project “innovative Public Organic food Procurement for Youth”, iPOPY, and is a revised version of a preliminary report published in the same report series in 2008. Organic and otherwise typical and certified food is supported by several Italian regions by regulations and guidelines demanding that municipalities must prioritize such food in their calls for tenders. This has contributed to make Italy a leading public consumer of organic food, serving about 1 million dishes of school food per day with at least some organic ingredients. In total, about 40% of the food consumed in Italian schools is organic, and 36% from otherwise certified agriculture (local speciality, integrated or fair trade). On full length school days, all pupils are served a warm meal with two dishes, commonly also a desert. The average payment is 3.86 Euro. Future challenges for the Italian school meals with their high share of organic food are to reduce the high amounts of food waste, partly incurred by the current system of food serving where all pupils get equal portions, served at a table. Further, non-food costs are a challenge, as they constitute 70 % of the total food costs. Means to ensure that municipalities and caterers follow the regional guidelines are also required, as well as support for the municipalities to design efficient calls for tenders. The communication about organic food in schools, e.g. as a part of the education, should be strengthened to increase the pupil’s understanding of the benefits of this farming practice for the environment

Reconfigurable Logic Interface Architecture for CPU-FPGA Accelerators

Programmable System-on-Chips (SoC) are a flexible solution to offload part of the computational power from CPU to FPGA and accelerate the execution time. In today ARM-based SoCs, CPU and FPGA are usually connected to each other through several different communication links based on AMBA standard. This paper presents two possible design as reconfigurable logic interface architectures to be employed as a high performance interface module in programmable logic accelerators. These designs provide us with programmability for bidirectional data communication paths between CPU memory-mapped master interface and FPGA. Our first proposed design offers up to 32 configurable registers while the other has up to 32 configurable FIFOs to be able to exchange larger data. Both of these architectures communicate to programmble logic accelerators through the data stream channels

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise: Designing a Computer Architecture via HLS)

Translating a system requirement into a low-level representation (e.g., register transfer level or RTL) is the typical goal of the design of FPGA-based systems. However, the Design Space Exploration (DSE) needed to identify the final architecture may be time consuming, even when using high-level synthesis (HLS) tools. In this article, we illustrate our hybrid methodology, which uses a frontend for HLS so that the DSE is performed more rapidly by using a higher level abstraction, but without losing accuracy, thanks to the HP-Labs COTSon simulation infrastructure in combination with our DSE tools (MYDSE tools). In particular, this proposed methodology proved useful to achieve an appropriate design of a whole system in a shorter time than trying to design everything directly in HLS. Our motivating problem was to deploy a novel execution model called data-flow threads (DF-Threads) running on yet-to-be-designed hardware. For that goal, directly using the HLS was too premature in the design cycle. Therefore, a key point of our methodology consists in defining the first prototype in our simulation framework and gradually migrating the design into the Xilinx HLS after validating the key performance metrics of our novel system in the simulator. To explain this workflow, we first use a simple driving example consisting in the modelling of a two-way associative cache. Then, we explain how we generalized this methodology and describe the types of results that we were able to analyze in the AXIOM project, which helped us reduce the development time from months/weeks to days/hours

From COTSon to HLS: translating timing into an architecture

Nowadays, the increasing core number benefits many workloads, but programming limitations to exploiting full performance still remain. A Data-Flow execution model is capable of taking advantage of the full parallelism offered by multicore systems. In such model, the execution can be decomposed in fine-grain threads named Data-Flow Threads (DF-Threads) so that each of them can execute only when their inputs are available. The execution overhead and power consumption is lowered thanks to the reduction of the data push-pull, as well as the burden of thread management